1. Field of the Invention
The present invention relates to a semiconductor device of a master slice type such as gate array, and particularly to a layout of bonding pads and buffers with a narrow pitch for wire bonding.
2. Description of the Prior Art
FIG. 8 is a view showing a chip configuration of a prior art semiconductor device of a master slice type using bonding pads and buffers arranged with a narrow pitch, and FIG. 9 is a partially enlarged view showing a configuration of the bonding pads and the buffers in a portion A surrounded by a broken line of FIG. 8. In these figures, reference numeral 1 indicates a bonding pad; 1a and 1b are an outer peripheral bonding pad and an inner peripheral bonding pad, respectively; reference numeral 2 is a buffer; reference numeral 3 is a wiring connecting each of the outer and inner peripheral pads 1a and 1b to the buffer 2; reference numeral 4 is a bonding pad for power supply; reference numeral 5 is a bonding pad for grounding; reference numeral 6 is a wiring connecting the power supply bonding pad 4 to a power supply; reference numeral 7 is a wiring connecting the grounding bonding pad 5 to the ground; and reference numeral 8 is an interconnection connecting the buffer 2 to an internal circuit. Further, character a indicates a pitch of each of the outer peripheral bonding pads 1a and the inner peripheral bonding pads 1b which are arranged in a staggered manner. The wirings include a signal line, a power supply line, and the ground line and, as shown in FIG. 7, the width of the wiring connecting a power supply or the ground to the buffer is generally larger than that of the wiring as the signal line. The reason for this is that since a large amount of current flows through the wiring as the power supply line or ground line, the wiring must ensure reliability against electromigration or the like by increasing its width.